library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity latch is
    port (
        i      : in  std_ulogic ;
        o      : out std_ulogic ;
        clk    : in  std_ulogic ;
		rst    : in  std_ulogic ;
        enable : in  std_ulogic 
        );
end latch;

architecture Behavioral of latch is
    signal data : std_ulogic := '0';
begin
    process(rst, clk, enable)
    begin
		if(rst='0') then
			data <= '0';
		else 
			if(clk'event and clk = '1' and enable = '1') then
				data <= i;
			end if;
		end if;
    end process;

    o <= data;
    
end Behavioral;

